Polymorphism in SystemVerilog
Polymorphism is one the most important OOP features used by the modern SystemVerilog test benches. This article explores a basic use case for this feature. Assume a testbench needs to monitor a number of DUT interfaces. Those monitors need to be able to reset their internal queues and some state variables whenever reset event happens during the simulation. In addition to resetting queues and variables, they all have one common reset requirement. Here's the code that reflects those assumptions: class mon_a; ... function common(); ... endfunction : common function mon_a_specific(); ... endfunction : mon_a_specific function reset(); $write("Reset A in progress...\n"); common(); mon_a_specific(); ... endfunction : reset endclass : mon_a class mon_b; ... function common(); ... endfunction : common function mon_b_specific(); ... endfunction : mon_b_specific function reset(); $write("Reset B in progress...\n"); common(); mon_b_specific(...